A dynamic random access memory (DRAM) cell, including a transistor and a capacitor, has a small cell size and a high operation speed. However, capacitor integration and scaling hamper reduction of DRAM cell area. For each DRAM memory generation, a constant capacitance value is targeted and requires a complicated stack or a deep-trench capacitor that leads to additional process steps and lessens compatibility with conventional, complementary metal oxide semiconductor (CMOS) structures.
In order to solve scaling problems, an alternative solution has been proposed where the conventional storage capacitor is replaced by a thin-film body of a silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistor (MOSFET). The memory storage mechanism for such a structure is based on the threshold voltage shift produced by majority carrier excess (accumulation) or deficit (depletion) in a floating-body. The cell utilizes the floating-body effect to store charge under the channel of an SOI transistor, which changes the transistor's threshold voltage, as a storage element. Since there is no body contact to instantly adjust a majority charge carrier concentration, equilibrium is established only after a relatively “long” period of time, which renders SOI memories attractive in terms of retention and refresh time.
As floating body cell size becomes smaller, the volume of the floating body decreases and the area between the source and the drain becomes closer, less charge is stored in the floating body resulting in charge loss being swept out by a forward bias effect caused by Shockley-Read Hall (SRH) recombination. Such charge loss may result in a decrease or loss of charge retention in the cell. In order to prevent this phenomenon in the conventional construction, the thickness of the SOI substrate is reduced as the cell size becomes smaller. However, as the thickness of the SOI substrate is reduced, the amount of charge accumulated in the floating body is decreased and the cell may be more susceptible to noise during operation. That is, the floating body effect is decreased, reducing the operating margin of the device.
There is a need for methods, structures and devices for increasing density and reliability in floating body transistors.